View SP5610_198198.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS
FEBRUARY 1997
ADVANCE INFORMATION
D.S. 3920 3.3
SP5610
1.3GHz BI-DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER
(Supersedes edition in 1996 Media IC Handbook, HB4599-1.0)
The SP5610 is a single chip frequency synthesiser designed for TV tuning systems. Control data is entered in the standard I2C BUS format. The device contains 1 addressable current limited output and 4 addressable bi-directional open collector ports one of which is a 3 bit ADC. The information on these ports can be read via the I2C BUS. The device has one fixed I2C BUS address and 3 programmable addresses, programmed by applying a specific input voltage to the P3 current limited output. This enables 2 or more synthesisers to be used in a system.
CHARGE PUMP CRYSTAL Q1 CRYSTAL Q2 SDA SCL [ I/O PORT P7 * I/O PORT P6 [ I/O PORT P5
1 2 3
16 15 14
DRIVE OUTPUT VEE RF INPUT RF INPUT VCC NC P3 OUTPUT PORT/ ADD SELECT I/O PORT P4 [
SP5610S
4 5 6 7 8
13 12 11 10 9
FEATURES J Complete 1.3GHz Single chip System J High Sensitivity RF Inputs J Programmable via I2C Bus J On Chip oscillator with 1kW negative resistance J Low power consumption (5V, 20mA) J Low Radiation J Phase Lock Detector J Varactor Drive Amp Disable J 5 Controllable Outputs J 5 Level ADC J Variable I2C BUS Address For Multi Tuner Applications J ESD Protection * J Switchable 512/1024 Reference Divider J Pin and Function Compatible with SP5510S [
* Normal ESD handling procedures should be observed.
MP16
[ = Logic level I/O * = 3-bit ADC input
Fig. 1 Pin connections - top view
ORDERING INFORMATION
SP5610S/KG/MPAS (Tubes) SP5610S/KG/MPAD (Tape and Reel)
[ The SP5510S does not have a switchable reference division ratio.
APPLICATIONS J Satellite TV when combined with SP4902 2.5GHz prescaler J Cable Tuning Systems J VCR's
SP5610 ELECTRICAL CHARACTERISTICS
Tamb= -40C to )85C, VCC=)4.5V to )5.5V. Reference frequency = 4MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Supply current Prescaler Input Voltage Prescaler Input Impedance Input Capacitance SDA, SCL Input High Voltage Input Low Voltage Input High Current Input Low Current Leakage Current SDA Output Voltage Pin 12 13, 14 13, 14 4, 5 4, 5 4, 5 4, 5 4, 5 4 1 1 1 16 500 6400 10 200 W ``Parallel Resonant" crystal. Resistance specified is max under all conditions "50 "170 "5 3 0 12.5 50 2 5.5 1.5 10 -10 10 0.4 Min Typ 20 Max 27 300 Units mA mVrms W pF V V mA mA mA V mA mA nA mA Conditions VCC = 4.5V to 5.5V 50MHz to 1.3GHz sinewave See Fig. 5.
Input Voltage = VCC Input Voltage = 0V When VCC = 0V Isink = 3mA Byte 4 Bit 2 = 0, Pin 1 = 2V Byte 4 Bit 2 = 1, Pin 1 = 2V Byte 4 Bit 4 = 1, Pin 1 = 2V Vpin 16 = 0.7V
Charge Pump Current Low Charge Pump Current High Charge Pump Output Leakage Current Charge Pump Drive Output Current Charge Pump Amplifier Gain Recommended Crystal series Resistance Crystal Oscillator Drive Level Crystal Oscillator Negative Resistance External Reference Input Frequency External Reference Input amplitude Output Ports P3 Sink Current P3 Leakage Current P4-P7 Sink Current P4-P7 Leakage Current Input Ports P3 Input Current High P3 Input Current Low P4,P5,P7 Input Voltage Low P4,P5,P7 Input Voltage High P6 Input Current High P6 Input Current Low
2 2 2 2 750 2 70
80 1000 8 200
mVp-p W MHz mVrms AC coupled sinewave AC coupled sinewave
10 10 9-6 9-6
0.7
1
1.5 10
mA mA mA
Vout = 12V Vout = 13.2V Vout = 0.7V Vout = 13.2V
10 10
mA
10 10 9,8,6 9,8,6 7 7 2.7
+10 -10 0.8
mA mA V V
Vpin 10 = 13.2V Vpin 10 = 0V
+10 -10
mA mA
See Table 3 for ADC Levels
2
SP5610
PRE AMP RF IN 13 14 PRESCALER 8 15 BIT PROGRAMMABLE DIVIDER FPD PHASE COMP F FCOMP DIVIDER 512/1024 OSC Q1 2 CRYSTAL Q2 3 1 CHARGE PUMP CHARGE PUMP DRIVE/ VARICAP OUT
POWER ON DET POR SCL 5 SDA 4 I2 C BUS TRANSCEIVER
15 BIT LATCH DIVIDE RATIO FL
LOCK DET DOWN
ADDRESS SELECT
3 BIT ADC
LEVEL 3 TTL COMP
5 BIT LATCH PORT INFORMATION 1
CONTROL DATA LATCHES AND CONTROL LOGIC
UP
16
CP
TO OS
4 4
PORT OUTPUT DRIVERS
12 15
V CC V EE
10 P3
9 P4
8 P5
7 P6
6 P7
Fig 2. Block diagram
3
SP5610 FUNCTIONAL DESCRIPTION
The SP5610 is programmed from an I2C Bus. Data and Clock are fed in on the SDA and SCL lines respectively as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. The Tables in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C Bus system. Table 4 shows how the address is selected by applying a voltage to P3. When the device receives a correct address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are programmed. When the device is programmed into the read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. the reference divider. The reference divider division ratio is switchable from 512 to 1024, and is controlled by bit 7 of byte 4 (TS0); a logic 1 for 512; a logic 0 for 1024. The SP5610 differs from the SP5510 in this respect, only 512 being available on the SP5510. Note, the comparison frequency is 7.8125kHz when a 4MHz reference is used, and divide by 512 is selected. Bit 2 of byte 4 of the programming data (CP) controls the current in the charge pump circuit, a logic 1 for "170mA and a logic 0 for "50mA allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. When the device is `frequency locked' the charge pump current is internally set to "50mA regardless of CP. Bit 4 of byte 4 (T0) disables the charge pump when it is set to a logic 1. Bit 8 of byte 4 (OS) switches the charge pump drive amplifier's output off when it is set to a logic 1. Bit 3 of byte 4 (T1) enables various test modes when set high. These modes are selected by bits 5, 6, 7 of byte 4 (TS2, TS1, TS0) as detailed in Table 5. When T1 is set low, TS2 and TS1 are assigned a `don't care' condition, and TS0 selects the reference divider ratio as previously described. Byte 5 programs the output ports P3 to P7; a logic 0 for a high impedance output and a logic 1 for low impedance (on).
WRITE MODE (Frequency Synthesis)
When the device is in write mode bytes 2+3 select the synthesised frequency, while bytes 4+5 control the output port states, charge pump, reference divider ratio and various test modes. Once the correct address is received and acknowledged, the first bit of the next byte determines whether that byte is interpreted as byte 2 or 4; a logic 0 for frequency information and a logic 1 for control and output port information. When byte 2 is received the device always expects byte 3 next. Similarly, when byte 4 is received the device expects byte 5 next. Additional data bytes can be entered without the need to re-address the device until an I2C stop condition is recognised. This allows a smooth frequency sweep for fine tuning or AFC purposes. If the transmission of data is stopped mid-byte (e.g. by another device on the bus) then the previously programmed byte is maintained. Frequency data from bytes 2 and 3 is stored in a 15-bit register and is used to control the division ratio of the 15-bit programmable divider. This is preceded by a divide-by-8 prescaler and amplifier to give excellent sensitivity at the local oscillator input, see Fig. 5. The input impedance is shown in Fig. 7. The programmed frequency can be calculated by multiplying the programmed division ratio by 8 times the comparison frequency FCOMP . When frequency data is entered, the phase comparator, via a charge pump and varicap drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phased locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin 2, or provided by an on-board crystal controlled oscillator. The comparison frequency FCOMP is derived from the reference frequency via
READ MODE
When the device is in read mode the status byte read from the device on the SDA line takes the form shown in Table 2. Bit 1 (POR) is the power-on reset indicator and is set to a logic 1 if the VCC supply to the device has dropped below 3V (at 25C), e.g. when the device is initially turned on. The POR is reset to 0 when the read sequence is terminated by a stop command. When POR is set high (at low VCC), the programmed information is lost and the output ports are all set to high impedance. Bit 2 (FL) indicates whether the device is phase locked, a logic 1 is present if the device is locked, and a logic 0 if the device is unlocked. Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports P7, P5 and P4 respectively. A logic 0 indicates a low level and a logic 1 a high level. If the ports are to be used as inputs they should be programmed to a high impedance state (logic 1). These inputs will then respond to data complying with TTL type voltage levels. Bits 6, 7 and 8 (A2, A1, A0) combine to give the output of the 5 level ADC. The ADC can be used to feed AFC information to the microprocessor from the IF section of the receiver, as illustrated in the typical application circuit.
APPLICATION
A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6. The SP5610 is function and pin equivalent to the SP5510 device apart from the switchable reference divider, and has much lower power dissipation, improved RF sensitivity and better ESD performance.
4
SP5610
MSB ADDRESS PROGRAMMABLE DIVIDER PROGRAMMABLE DIVIDER CONTROL DATA IO PORT CONTROL DATA 1 0 27 1 P7 1 214 26 CP P6 0 213 25 T1 P5 0 212 24 T0 P4 0 211 23 TS2 P3 MA1 210 22 TS1 X MA0 29 21 TS0 X
LSB 0 28 20 OS X A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5
Table 1 Write data format (MSB is transmitted first)
ADDRESS STATUS BYTE 1 POR 1 FL 0 I2 0 I1 0 I0 MA1 A2 MA0 A1 1 A0 A A Byte 1 Byte 2
Table 2 Read data format (MSB is transmitted first)
A: MA1, MA0: CP: T1: T0: TS2, TS1, TS0: OS: P7,P6,P5,P4,P3: POR: FL: I2, I1, I0: A2, A1, A0: X: Acknowledge bit Variable address bits (see Table 4) Charge pump current select Test mode enable Charge pump disable Operation mode control bits (see Table 5) Varactor drive Output disable Switch Control output states Power On Reset indicator Phase Lock detect Flag Digital information from Ports P7, P5 and P4, respectively 5 Level ADC data from P6 (see Table 3) Don't care
A2 1 0 0 0 0
A1 0 1 1 0 0
A0 0 1 0 1 0
Voltage input to P6 0.6VCC to 13.2V 0.45VCC to 0.6VCC 0.3VCC to 0.45VCC 0.15VCC to 0.3VCC 0 to 0.15VCC
MA1 0 0 1 1
MA0 0 1 0 1
Voltage input to P3 0 - 0.2VCC ALWAYS VALID 0.3VCC - 0.7VCC 0.8VCC - 13.2V
Table 4 Address selection
Table 3 ADC levels
T1 0 0 1 1 1 1 1
TS2 X X 0 0 1 1 1
TS1 X X 0 1 0 0 1
TS0 0 1 X X 0 1 X
OPERATION MODE DESCRIPTION Normal operation, test modes disabled, reference divider ratio=1024 Normal operation, test modes disabled, reference divider ratio=512 Charge pump source (down). Status byte bit FL set to 0 Charge pump sink (up). Status byte bit FL set to 1 Ports P4,P5,P6,P7 set to state X Port P7=FPD/2; P4,P5,P6 set to state X Port P7=FPD; P6=FCOMP; P4, P5 set to state X
X=don't care For further details of test modes see Table 6.
Table 5 Operation modes Fig. 3 Data formats
5
SP5610
+30V +12V +5V IF SECTION AFC OUTPUT TUNER 22k P7 BAND INPUTS P5 P4 P3
9 10 8 7
IF SIGNAL
P6 SCL I2 C BUS SDA 4MHz CRYSTAL 18p 180n
SP5610S
11 12
6 5 4 3 2 1
OSCILLATOR OUTPUT
1n
13 14
CONTROL MICRO
1n 0.1m VARICAP INPUT 47k 10k 10nF VT
15 16
39n 22k BCW31
Fig. 4 Typical application
300
37.5 VIN (mV RMS INTO 50W) 25 12.5
OPERATING WINDOW
50
500
1000 FREQUENCY (MHz)
1300 1500
Fig. 5 Typical input sensitivity
6
SP5610
VCC V REF CHARGE PUMP 3K 3K
RF INPUTS 150 OS (O/P DISABLE) DRIVE OUTPUT
RF input
Loop amplifier
VCC
VCC 67k SCL/SDA
3k
CRYSTAL Q1 ACK CRYSTAL Q2 SDA ONLY
Reference oscillator
SCL and SDA input
VCC VCC
PORT 3k 3k 12k
PORT
Ports P7 - P4
Port P3
Fig. 6 Input/output interface circuits
7
SP5610
+j1 +j0.5 +j2
+j0.2
+j5
0
0.2
0.5
1
2
5
1.25GHz
-j0.2 -j5
-j0.5
-j2 -j1
FREQUENCY MARKER STEP = 250MHz
S11:Z0 = 50W NORMALISED TO 50W
Fig. 7 Typical input impedance
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE and pin 3 at 0V. Value Parameter Supply voltage RF input voltage Port voltage Pin 12 13, 14 6-10 6-9 10 6-10 13, 14 1 16 2 4, 5 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 55 - 0.3 - 0.3 - 0.3 Min - 0.3 Max 7 2.5 14 6 14 50 VCC +0.3 VCC+0.3 VCC+0.3 VCC+0.3 6 +150 +150 111 41 150 ALL 4 Units V Vp-p V V V mA V V V V V C C C/W C/W mW kV All ports off MIL STD 883C TM 3015 Port in off state Port in on state Port in on state Conditions
Total port output current RF input DC offset Charge Pump DC offset Drive DC offset Crystal oscillator DC offset SDA,SCL input voltage Storage temperature Junction temperature MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case Power consumption at 5.5V ESD protection
8
SP5610 APPLICATION NOTES
A generic set of application notes AN168 for designing with synthesisers such as the SP5610 has been written. This covers aspects such as loop filter design, decoupling and I2C bus radiation problems. This application note is featured in the Media October 1995 IC Handbook. A generic test/demo board has been produced which can be used for the SP5610. A circuit diagram and layout for the board is shown in Figs. 8 and 9. The board can be used for the following purposes: (A) Measuring RF sensitivity performance. (B) Indicating port function. (C) Synthesising a voltage controlled oscillator. (D) Testing of external reference sources. The programming codes relevant to these tests are shown in Table 6.
+5V
+30V
+12V
C8 EXTERNAL REFERENCE MODE SELECT R11 3K0 S1 R12 1K0 S2 SKT2 C6 10nF* *(NOT FITTED) C2 C1 X1 4MHz 18pF TP1 DATA/SDA C12 100pF C13 100pF P1 P4 R1 4K7 R2 4K7 R3 4K7 R4 4K7 R5 4K7 R6 4K7 220nF R7 22K
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
C9 C7/C8/C9 = 100nF C7
C3 47nF
R8 22K R9
R10
P3 VAR GND
10K 47K C14 T1 10nF 2N3904 C4 1nF
RF INPUT C5 1nF C10 1nF
CLOCK/SCL ENABLE/ ADDRESS SEL
R14 22K T2 2N3906
R13 12K
D1
D2
D3
D4
PIN NO: 6
7
89 C11 1nF
D5
10
11
FOR EXTERNAL REFERENCE CAPACITOR C6 SHOULD BE FITTED AND CAPACITOR C1 REMOVED FROM THE TEST BOARD
Fig. 8 Test board
D6
9
SP5610
P2
TP1 = PIN 3 DC BIAS P3 TP1
P4 P1
Top view (Ground plane)
Underside (surface mount components side)
NOTES: CIRCUIT SCHEMATIC IS SHOWN IN FIG. 8. ALL SURFACE MOUNT COMPONENTS MOUNTED ON UNDERSIDE OF BOARD
Fig. 9 Test board (layout)
10
SP5610 TEST MODES
As explained earlier in the data sheet, the device can be programmed into a number of test modes. These are invoked by programming the following HEX codes into Byte 4. The most commonly used codes are shown in Table 6 HEX CODE (BYTE 4) DESCRIPTION CP HI MODE Normal operation, REF DIV =1024 Normal operation, REF DIV = 512 Charge Pump Source (Down), FL SET to 0 Charge Pump Sink (up), FL SET to 1 Port P7 = FPD/2 Port P7 = FPD; P6 = FCOMP Charge Pump Disable, REF DIV 512 Varactor Line Disable, REF DIV 512 Charge Pump and Varactor Line Disable, REF DIV 512 CC CE E2 E6 EA EE DE CF DF CP LO MODE 8C 8E A2 A6 AA AE 9E 8F 9F
Table 6 Useful test modes.
Other codes will also apply due to `Don't Care' conditions, which are assumed to be 1 in the above Table. NOTE: When looking at FPD or FCOMP signals from Ports P7 and P6, Byte 4 should be sent twice, firstly to set the desired reference divider ratio, (see Table 6) then secondly to switch on the chosen test mode. The pulses can then be measured by simply connecting an oscilloscope or counter to the relevant output pin on the test board.
11
SP5610
9.80/10.01 (0.386/0.394) 0.69 (0.027) NOM AT 4 PLACES 3.80/4.00 (0.150/0.157)
16 LEAD MINIATURE PLASTIC MP16
PIN 1 PIN 1 IDENTIFICATION
1.27 (0.050) NOM PIN SPACING 1.35/1.75 (0.053/0.069) 0.25/0.51 (0.010/0.020) X45 8MAX 0.41/1.27 (0.016/0.050) 5.80/6.20 (0.228/0.244) 0.19/0.25 (0.007/0.010)
0.35/0.49 (0.014/0.019)
0.10/0.25 (0.004/0.010)
Purchase of GEC Plessey I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the standard I2C Standard Specification as defined by Philips.
All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire United Kingdom SN2 2QW. Tel: (01793) 518000 Fax: (01793) 518411 Internet: http//www.gpsemi.com CUSTOMER SERVICE CENTRES F FRANCE & BENELUX Les Ulis Cedex Tel: (1) 69 18 90 00 Fax: (1) 64 46 06 07 F GERMANY Munich Tel: (089) 3609 06 0 Fax: (089) 3609 06 55 F ITALY Milan Tel: (02) 6607151 Fax: (02) 66040993 F JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 KOREA Seoul Tel: (2) 5668141 Fax: (2) 5697933 F NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023 F SOUTH EAST ASIA Singapore Tel: 3827708 Fax: 3828872 F SWEDEN Stockholm Tel: (8) 702 97 70 Fax: (8) 640 47 36 F TAIWAN, ROC Taipei Tel: (2) 5461260 Fax: (2) 7190260 F UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 518527/518566 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world-wide.
GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 5576/6231 Fax: (408) 438 5576
E GEC Plessey Semiconductors 1997 Publication No. D.S. 3920 Issue No. 3.3 February 1997 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM
This publication is issued to provide information only, which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design, or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
12
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of SP5610

	To Download SP5610 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .